Texas Instruments TMS320TCI6486 - Manual (Page 59)

www.ti.com EMAC Functional Architecture
A MAC address location in RAM is 53 bits wide and consists of:
• 48 bits of the MAC address
• 3 bits for the channel to which a valid address match will be transferred. The channel is a don't care if
the MATCHFILT bit is cleared.
• A valid bit
• A match or filter bit
First, write the index into the address RAM in the MACINDEX register to start writing a MAC address.
Then write the upper 32 bits of the MAC address (MACADDRHI register), and then the lower 16 bits of
MAC address with the VALID and MATCHFILT control bits (MACADDRLO). The valid bit should be
cleared for the unused locations in the receive address RAM.
The most common uses for the receive address sub-module are:
• Set EMAC in promiscuous mode, using the RXCAFEN and RXPROMCH bits in the RXMBPENABLE
register. Then filter up to 32 individual addresses, which can be both unicast and/or multicast.
• Disable the promiscuous mode (RXCAFEN = 0) and match up to 32 individual addresses, multicast
and/or unicast.
2.11.4 Hardware Receive QOS Support
Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier
format and the associated Tag Control Information (TCI) format priority field. When the incoming frame
length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Encoded Tag
Protocol Type. The two octets immediately following the protocol type contain the 16-bit TCI field. Bits
15-13 of the TCI field contain the received frames priority (0 to 7). The received frame is a low-priority
frame if the priority value is 0 to 3. The received frame is a high-priority frame if the priority value is 4 to 7.
All frames that have a length/type field value not equal to 81.00h are low-priority frames.
Received frames that contain priority information are determined by the EMAC as:
• A 48-bit (6 bytes) destination address equal to:
– The destination station's individual unicast address
– The destination station's multicast address (MACHASH1 and MACHASH2 registers)
– The broadcast address of all ones
• A 48-byte (6 bytes) source address
• The 16-bit (2 bytes) length/type field containing the value 81.00h
• The 16-bit (2 bytes) TCI field with the priority field in the upper 3 bits
• Data bytes
• The 4-bytes CRC
The RXFILTERLOWTHRESH and the RXnFREEBUFFER registers are used in conjunction with the
priority information to implement receive hardware QOS. Low-priority frames are filtered if the number of
free buffers (RXnFREEBUFFER) for the frame channel is less than or equal to the filter low threshold
(RXFILTERLOWTHRESH) value. Hardware QOS is enabled by the RXQOSEN bit in the RXMBPENABLE
register.
2.11.5 Host Free Buffer Tracking
The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and
promiscuous) if receive QOS or receive flow control is used. Disabled channel free buffer values are don't
cares. During initialization, the host should write the number of free buffers for each enabled channel to
the appropriate RXnFREEBUFFER register. The EMAC decrements the appropriate channel's free buffer
value for each buffer used. When the host reclaims the frame buffers, the host should write the channel
free buffer register with the number of reclaimed buffers (write to increment). There are a maximum of 65
535 free buffers available. The RXnFREEBUFFER registers only need to be updated by the host if receive
QOS or flow control is used.
59 SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO
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