Texas Instruments TMS320TCI6486 - Manual (Page 113)

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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 61 and described in
Table 55 .
Figure 61. MAC Interrupt Mask Set Register (MACINTMASKSET)
31 16
Reserved
R-0
15 2 1 0
HOST STAT
Reserved
MASK MASK
R-0 R/WS-0 R/WS-0
LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset
Table 55. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTMASK Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0 STATMASK Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
113 SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO
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