Texas Instruments TMS320TCI6486 User Manual
Page 27
TXD
TX_SYNC
TX_CLK
RXD
RX_SYNC
RX_CLK
MHZ_125_CLK
Device #1
TXD
TX_SYNC
TX_CLK
RXD
RX_SYNC
RX_CLK
MHZ_125_CLK
Device #2
TXD
TX_SYNC
TX_CLK
RXD
RX_SYNC
RX_CLK
MHZ_125_CLK
Device #n
125-MHz
zero-delay
clock buffer
125-MHz
XO
Low-skew
buffer
Zero-delay
clock buffer
External
logic
element
S3MII
multi-PHY
TX_CLK
TX_SYNC
P0_TXD
P0_RXD
P1_TXD
P1_RXD
Pn_TXD
Pn_RXD
RX_SYNC
RX_CLK
www.ti.com
EMAC Functional Architecture
Figure 7. S3MII Multi-PHY Configuration
27
SPRUEF8F – March 2006 – Revised November 2010
C6472/TCI6486 EMAC/MDIO
Copyright © 2006–2010, Texas Instruments Incorporated
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