Texas Instruments MSP50C6xx - Manual (Page 73)

Digital-to-Analog Converter (DAC)
3-9 Peripheral Functions
3.2 Digital-to-Analog Converter (DAC)
The MSP50C6xx incorporates a two-pin pulse-density-modulated DAC which
is capable of driving a 32-
Ω
loudspeaker directly. To drive loud speakers other
than 32
Ω
, an external impedance-matching circuit is required.
3.2.1 Pulse-Density Modulation Rate
The rate of the master clock (MC) determines the pulse-density-modulation
(PDM) rate, and this governs the output sampling-rate and the achievable
DAC resolution. In particular, the sampling rate is determined by dividing the
PDM rate by the required resolution:
Output sampling rate = PDM Rate
÷
2 (# DAC resolution bits)
PDM Rate #DAC resolution bits
Set in ClkSpdCtrl register Set in DAC control register
Address 0x3D Address 0x34
For example, a 9 bit PDM DAC at 8 kHz sampling rate requires a PDM rate of
4.096 MHz.
There are four sampling rates which may be used effectively within the
constraints of the MSP50C6xx and the various software vocoders provided by
Texas Instruments. These are: 7.2 kHz, 8 kHz, 10 kHz, and 11.025 kHz. Other
sampling rates, however, may also be possible.
From the MC to the PDM clock, there is an optional divide-by-two in frequency.
This option is controlled by the PDM clock divider in the interrupt/general
control register. This means that the PDM rate can be set to run between
131.07 kHz and 33.554 MHz in 131.07 kHz steps (the same as the MC). Or,
the PDM rate can be set to run between 65.536 kHz and the maximum
achievable CPU frequency (see the MSP50C6xx data sheet (SPSS023),
Electrical Specifications) in 65.536-kHz steps. The PDM clock divider
determines which of these two ranges apply. Within these ranges, it is the
PLLM that sets the rate: ClkSpdCtrl, 0x3D. Refer to Section 3.2.3, PDM Clock
Divider, for more information regarding the PDM clock divider and the
available combinations of CPU clock rates vs sampling rates. (Section 2.9.3,
Clock Speed Control Register, contains more details regarding the PLLM.)
3.2.2 DAC Control and Data Registers
The resolution of the PDM-DAC is selected using the control bits in the DAC
control register (address 0x34). The available options are 8, 9, or 10 bits of res-
olution. Bits 0 and 1 in the DAC control register control this option: