Texas Instruments MSP50C6xx - Manual (Page 46)

Interrupt Logic
2-22
When the device is powered up, the hardware initialization circuit reads the
value stored in the block protection word. The value is then loaded to an inter-
nal register and the security state of the ROM is identified. Until this occurs,
execution of any instructions is suspended.
The same initialization sequence is executed before entry into the special
test-modes available on the P614 and C6xx (EPROM mode, emulation mode,
and trace mode). This insures that the protection scheme is always in force
when running the processor in one of these modes. A dedicated circuit
ensures that a switch between emulation mode and trace mode cannot occur
without going through the initialization (security check). This forces all look-up
tables and long constant references to originate from an external program
source, when in emulation mode. It is possible to switch from trace mode to
emulation mode by lowering V
PP
, but this transition, by design, does not
jeopardize code security.
2.6.5 Macro Call Vectors
Macro call vectors are similar to CALL instructions except they take an 8-bit
address. The upper 8 bits is always 7Fh. See Section 4.14.84, VCALL, for
more information on the VCALL instruction.
2.7 Interrupt Logic
An eight-level interrupt system is included as part of the C6xx’s core processor.
The initialization and control of these interrupts is governed by the following
components: the global interrupt enable, the interrupt flag register, the
interrupt mask register, and the interrupt service branch. Each of these is
described below.
Interrupts must be globally enabled using the INTE instruction, and they are
globally disabled using the INTD instruction. INTE sets the global interrupt
enable bit, and INTD clears the global interrupt enable bit. The state of this bit
specifically determines whether any interrupt service branches will be taken.
The global interrupt enable appears as bit 4 within the status register (STAT).
Note:
To ensure proper executions of the INTD instruction, it is recommended that
the INTD instruction be prescaled with a RPT 2–2 instruction.
Each interrupt level waits for the conditions of its trigger event (refer to
Figure 2–8). At the time that a trigger event occurs, the respective bit is