Texas Instruments MSP50C6xx - Manual (Page 57)

Reduced Power Modes
2-33 MSP50C6xx Architecture
enable bit for TIMER2. Setting the enable bit enables the TIMER, i.e., starts
count-down running. Clearing the enable bit disables the TIMER, i.e., stops
the count-down. The default setting after a RESET LOW is zero: both TIMERs
disabled. Refer to Section 3.4, Interrupt/General Control Register, for sum-
mary information regarding the IntGenCtrl.
The TIMER enable bits may be used to start and stop the TIMERs repeatedly
in software. Switching the enable bit from 1 to 0 stops the TIMER, but the
current value in the count-down register is retained. When the enable bit is
subsequently switched from 0 to 1, count-down then resumes from the held
value. The following procedure outlines one (of many) possible ways to start
the TIMERs. TIMER2 is given as an example:
1) Select the TIMER2 clock source: 1/2 MC or RTO/CRO (bit 9 of the Int-
GenCtrl, address 0x38).
2) Clear the TIMER2 enable (bit 11 in the IntGenCtrl).
3) Load the count-down register (TIM2) with the desired period value ahead-
of-time. This prepares TIM2 for counting, and also loads the period regis-
ter (PRD2) with its value.
4) Be sure the TIMER2 interrupt (INT2) has been enabled for service (set bit
2 of IntGenCtrl).
5) Flip the TIMER2 enable bit from 0 to 1, at the precise time you want count-
ing to begin.
2.10 Reduced Power Modes
The power consumption of the C6xx is greatest when the DAC circuitry is
called into operation, i.e., when the synthesizer speaks. There are, however,
a number of reduced power modes (sleep states) on the C6xx which may be
engaged during quiet intervals.
The performance and flexibility of the reduced power modes make the C6xx
ideal for battery powered operation. Refer to data sheets for the MSP50C6xx
devices.
The reduced power state on the C6xx is achieved by a call to the IDLE
instruction. The idle state is released by some interrupt event. Different modes
(or levels) of reduced-power are brought about by controlling a number of
different core and periphery components on the device. These components
are independently enabled/disabled before engaging the IDLE instruction.
The number of subsystems left running during sleep directly impacts the