Renesas M3062PT2-EPB - Manual (Page 85)

M3062PT2-EPB User’s Manual 4. Hardware Specifications
REJ10J0868-0200 Rev.2.00 January 16, 2006
4.4 Connection Diagrams
Figure 4.7 shows a connection diagram of the M3062PT2-EPB. This connection diagram mainly show the circuit to be
connected to the user system. The circuits not connected to the user system such as the emulator’s control system are omitted.
Tables 4.8 and 4.9 show IC electric characteristics of this product for reference purpose.
Figure 4.7 Connection diagram
IC20
M16C/62P
I/O Emulate
P67--P60
P77--P70
P84--P80
P97--P90
P117--P110
P127--P120
P137--P130
P141, P140
P67--P60
P77--P70
P84--P80
P97--P90
P117--P110
P127--P120
P137--P130
P141, P140
P85/NMI*
P86/Xcout
P87/Xcin
P85/NMI*
P86/Xcout
P87/Xcin
CNVss
BYTE
RESET*
Xin
100 Ω
510k Ω Vcc1
*
74HC4066
74HC4066
510k Ω Vcc1
510k Ω Vcc1
*
*
*
*
IC8
Port Emulation
FPGA
P07--P00
51k Ω Vcc2
P27--P20
51k Ω Vcc2
AN7--AN0
74HC4066
74HC4066
51k Ω Vcc1
P107--P100
74HC4066
74HC4066
7WH125
*
P17--P15
51k Ω Vcc2
*: Connected to the inside of the emulator.
Pullup registers indicated by
dashed line: socket mounted.
R3：0 Ω
Vcc2
R2：0 Ω Vcc2
Vcc2
510k Ω Vcc1
Xout
74HC4066
Xout
51k Ω Vcc2
Vcc2
P14--P10
P37--P30
P47--P40
P57--P50
INT5*--INT3*
User
sy
st
em
74HC4066
*
Page 85 of 102