ProSoft Technology MVI56E-MNET/MNETXT - Manual (Page 43)

MVI56E-MNET / MNETXT ♦ ControlLogix Platform Configuring the MVI56E-MNET Module
Modbus TCP/IP Interface Module User Manual
ProSoft Technology, Inc. Page 43 of 181
April 23, 2014
Write Register Start
0 to 4999
The Write Register Start parameter specifies the start of the Write Data area in
module memory. Data in this area will be transferred in from the processor.
Note: Total user database memory space is limited to the first 5000 registers of module memory,
addresses 0 through 4999. Therefore, the practical limit for this parameter is 4999 minus the value
entered for Write Register Count, so that the Write Data Area does not try to extend above address
4999. Read Data and Write Data Areas must be configured to occupy separate address ranges in
module memory and should not be allowed to overlap.
Write Register Count
0 to 5000
The Write Register Count parameter specifies the size of the Write Data area of
module memory and the number of registers to transfer from the processor to
this memory area, up to a maximum value of 5000 words.
Note: Total Read Register Count and Write Register Count cannot exceed 5000 total registers.
Read Data and Write Data Areas must be configured to occupy separate address ranges in
module memory and should not be allowed to overlap.
Failure Flag Count
0 through 65535
This parameter specifies the number of successive transfer errors that must
occur before halting communication on the application port(s). If the parameter is
set to 0, the application port(s) will continue to operate under all conditions. If the
value is set larger than 0 (1 to 65535), communications will cease if the specified
number of failures occur.
Initialize Output Data
0 = No, 1 = Yes
This parameter is used to determine if the output data for the module should be
initialized with values from the processor. If the value is set to 0, the output data
will be initialized to 0. If the value is set to 1, the data will be initialized with data
from the processor. Use of this option requires associated ladder logic to pass
the data from the processor to the module.