Chapter 3 bios description – Foxconn 865A05-G-6ELS User Manual
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Chapter 3 BIOS Description
865A05 G/P/PE/GV User Manual
Advanced Chipset Features
v
DRAM Timing Selectable (Default: By SPD)
This option is used to set the signal time sequence of the DRAM. The
“By SPD”
DRAM speed is controlled by the DRAM data register, and the
“By Manual”
DRAM speed is controlled by the user.
v
CAS Latency Time (Default: 2.5)
It sets the delay time for DRAM and CAS signals.
v
Active to Precharge Delay (Default: 7)
It sets the precharge delay for DRAM.
v
DRAM RAS# to CAS# Delay (Default: 3)
It sets the delay time between the RAS and CAS.
v
DRAM RAS# Precharge (Default: 3)
It sets the precharge time for DRAM and RAS signals.
v
Memory Frequency For (Default: Auto)
It sets the frequency for memory.
Note: The operating frequency will be 320MHz when a 800MHz CPU and
DDR333MHz are used jointly.
v
System BIOS Cacheable (Default: Enabled)
This option is used to determine whether the system BIOS is written into the
buffer memory. The available setting values are: Disabled and Enabled.
Advanced Chipset Features Setup
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