Comtech EF Data SDM-100A - Manual (Page 125)

SDM-100A Satellite Modem Theory of Operation
Rev. 0 4–9
4.2.4 Sequential Decoding Theory
The sequential decoder is used in closed network applications, typically in Frequency
Division Multiple Access (FDMA) satellite communications systems. The sequential
decoder is optional firmware that plugs onto the demodulator/M&C/interface board.
When not installed, sequential encoding and decoding types may not be selected.
Refer to Figure 4-5 for a block diagram of the sequential decoder.
The sequential decoder also works in conjunction with the convolutional encoder at the
transmitting modem to correct bit errors in the received data stream from the
demodulator.
The sequential decoder processes 2-bit quantized I&Q channel data symbols from the
demodulator. This data is assumed to be a representation of the data transmitted,
corrupted by additive white Gaussian noise. The decoder’s task is to determine which bits
have been corrupted by the transmission channel, and correct as many as possible. The
means to do this is provided by the parity bits added by the encoder to the data stream
prior to transmission.
The possible sequences of bits, including parity output by the encoder, are listed on a
code tree. The decoder uses the parity bits and knowledge of the code tree to determine
the most likely correct sequence of data bits for a given received sequence.
The search proceeds from a node in the code tree by choosing the branch with the highest
metric value (highest probability of a match between the received data and a possible
code sequence). The branch metrics are added to form the cumulative metric. As long as
the cumulative metric increases at each node, the decoder assumes it is on the correct
path, and continues forward. If the decoder makes a wrong decision, the cumulative
metric will decrease rapidly as the error propagates through the taps of the parity
generator. In this case, the decoder tries to back up through the data to the last node
where the metric was increasing, then take the other branch.
In an environment with severe errors, the decoder will continue to search backwards for a
path with an increasing metric until it either finds one, runs out of buffered data, or runs
out of time and must deliver the next bit to the output.
The decoder processes data at a fixed rate, which is much higher than the symbol rate of
the input data. This allows it to evaluate numerous paths in its search for the most likely
one during each symbol time.
Data enters the input RAM of the decoder from the demod processor in 2-bit soft
decision form for both I&Q channels, as shown in the block diagram (Figure 4-5). The
input RAM buffers the data to provide history for the backward searches. Data from the
RAM passes through the Ambiguity Corrector, which compensates for the potential 90
°
phase ambiguity of the demodulator.