Power distribution system, Power distribution system –63 – Altera 100G Development Kit, Stratix V GX Edition User Manual
Page 71

Chapter 2: Board Components
2–63
Power
August 2012
Altera Corporation
100G Development Kit, Stratix V GX Edition
Reference Manual
Power Distribution System
A 19-V DC input from the DC power jack (J2) powers up the development board.
shows the power distribution system on the development board.
Figure 2–10. Power Distribution System
14 - 20 V
DC INPUT
12 V ATX Power
MAX II, USB, CLOCKS,
CFP, User IO
Fan
2.5V_AUX
QDR II, DDR3, VCC_IO
2.5V_VCCA_PLL
VCCT_GXB
VCCR_GXB
2.5VIO_PD_CLK_PGM
1.5V_VCCPT
VCCH_GXB
VCC, VCCHSSI, VCCHIP
QSFP, SFP
VCCD_PLL
CFP Translators
Flash, QDR II
VCCA_GXB
LTM4601
Switcher
LTM4601
Switcher
LT1374
Switcher
LTM4601
Switcher
LTM4601
LTM4600
Switcher
Switcher
1.5 V
12 V
5.0 V
2.5 V
1.0 V
2.5 V
1.5 V
1.0 V
1.5 V
3.3 V
0.9 V
VTT, VREF
0.75 V
12 V
1.5 V
1.2 V
1.8 V
3.3 V
3.0 V
5.0 V
LTC3026
Linear
Linear
LTC3026
Linear
Ethernet PHY
1.1 V
LTC3026
Linear
LT3070
Linear
LTC3026
Linear
LTC3026
LTC3026
Linear
LTC3026
Linear
Linear
Linear
MIC65902
Linear
MIC65902
MIC49500
TPS5100
Regulator
LTM4627
Switcher
Ideal Diode
Mux
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)