Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 46)

2–38 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
33 CFP_PRG_ALRM1 2.5-V LVCMOS AG34
Programmable alarm 1 set via MDIO and MSA for
RXS, RX CDR lock indication.
0: Locked
1: Unlocked
34 CFP_PRG_ALRM2 2.5-V LVCMOS AP33
Programmable alarm 2 set via MDIO and MSA
(HIPWR_ON).
0: Module not powered-up
1: Module power-up completed
35 CFP_PRG_ALRM3 2.5-V LVCMOS AK32
Programmable alarm 3 set via MDIO and MSA for
module initialization (MOD_READY)
0: Initialization not done
1: Initialization completed
30 CFP_PRG_CNTL1 2.5-V LVCMOS AU21
Programmable control 1 set via MDIO and MSA
for TX and RX IC reset (TRXIC_RSTn)
0: Reset
1 or NC: Enabled or not in use
31 CFP_PRG_CNTL2 2.5-V LVCMOS AG32
Programmable control 2 set via MDIO and MSA
for hardware power interlock (LSB).
00: < 8 W
01: < 16 W
10: < 24 W
11 or NC: > 24 W or not in use
32 CFP_PRG_CNTL3 2.5-V LVCMOS AW21
Programmable control 3 set via MDIO and MSA
for hardware power interlock (MSB).
00: < 8 W
01: < 16 W
10: < 24 W
11 or NC: > 24 W or not in use
147 CFP_REFCLK_N LVDS — Input reference clock
146 CFP_REFCLK_P LVDS — Input reference clock
40 CFP_RX_LOS 2.5-V LVCMOS BB20
Receiver loss of optical signal on any channel.
0: Normal condition.
1: Signal loss.
77 CFP_RX_MCLK_N CML — Only used for optical waveform testing
76 CFP_RX_MCLK_P CML — Only used for optical waveform testing
79 CFP_RX_P0 1.5-V PCML AP2 Receive XCVR pair 0 to FPGA
80 CFP_RX_N0 1.5-V PCML AP1 Receive XCVR pair 0 to FPGA
82 CFP_RX_P1 1.5-V PCML AM2 Receive XCVR pair 1 to FPGA
83 CFP_RX_N1 1.5-V PCML AM1 Receive XCVR pair 1 to FPGA
85 CFP_RX_P2 1.5-V PCML AK2 Receive XCVR pair 2 to FPGA
Table 2–31. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
(J25)
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin
Number
Description