Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 12)

2–4 Chapter 2: Board Components
Board Overview
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
U20 LVPECL to LVDS buffer 644.53125MHz LVDS clock buffer.
U47, U48,
U49 Differential to LVDS clock
buffer Differential clock buffer (2 to 4) distributed to CMU and dedicated differential
clock inputs on the vertical banks of the FPGA.
U21
Differential divide-by-4
clock divider
Divide-by-4 clock circuit to provide the required clock to CFP.
U30
Differential to LVDS clock
buffer Differential clock buffer (2 to 6) distributed to CMU of the FPGA and to clock
dividers for the optical clock.
U44, U22,
U53 External programmable
PLLs
On-board programmable PLL clock source with buffers.
X1
644.53125-MHz LVPECL
oscilator
644.53-MHz clock to the FPGA transceivers.
X2 100-MHz oscillator 100-MHz oscillator for the MAX II device’s PFL function.
X3 25-MHz oscillator 25-MHz oscillator for the Ethernet controller.
X4 125-MHz oscillator 125-MHz oscillator for the Ethernet interface.
X5 50-MHz oscillator 50-MHz NIOS II CPU clock (CMOS).
Y1, Y2, Y3 25-MHz crystal clock 25-MHz reference clock for external PLLs.
General User Input and Output
D39–D42 User LEDs Four green LEDs for the MAX II CPLD EPM2210 System Controller.
D43–D50 FPGA LEDs Eight green LEDs for the FPGA.
J64 Character LCD Connector which interfaces to the 16 character × 2 line LCD module.
S2–S4 User push buttons User push buttons that connect to the MAX II CPLD EPM2210 System Controller.
S9–S12 FPGA user push buttons User push buttons that connect to the Stratix V GX device.
SW4
Bank-of-eight user DIP
switch
User DIP switch that connects to the FPGA.
SW5
Bank-of-eight user DIP
switch
User DIP switch that connects to the MAX II CPLD EPM2210 System Controller.
Memory Devices
U24-U29,
U31-U36 DDR3 x32 port Twelve 256-Mb independent DDR3 memory with 16-bit data bus, combining to
make six 32-bit DDR3 interface.
U40 QDR II x18 port One 72-Mb independent QDR II memory with 18-bit data bus.
U41 QDR II x36 port One 72-Mb independent QDR II memory with 36-bit data bus.
U60 Flash memory
Synchronous burst mode flash device which provides 1-Gb non-volatile memory.
This device is located under the character LCD.
Components and Interfaces
J33 QSFP interface QSFP XCVR interface (4 channels): QSFP0_TX_P/_N[3:0], QSFP0_RX_P/_N[3:0]
J19 QSFP interface QSFP XCVR interface (4 channels): QSFP1_TX_P/_N[3:0], QSFP1_RX_P/_N[3:0]
J25 CFP interface CFP XCVR interface (10 channels): CFP_TX_P/_N[9:0], CFP_RX_P/_N[9:0]
J10 SFP+ interface Four SFP+ XCVR interfaces.
J61 I/O connector General purpose expansion connector with 10 user-definable I/Os that connect to
the MAX II CPLD EPM2210 System Controller.
Table 2–1. Stratix V GX 100G Development Board Components (Part 3 of 4)
Board
Reference
Type Description