Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 49)

Chapter 2: Board Components 2–41
Components and Interfaces
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
D6 INT_TX_P1 1.5-V PCML AG41 Transmit XCVR pair 1 from FPGA
E6 INT_TX_N1 1.5-V PCML AG42 Transmit XCVR pair 1 from FPGA
D8 INT_TX_P2 1.5-V PCML AC41 Transmit XCVR pair 2 from FPGA
E8 INT_TX_N2 1.5-V PCML AC42 Transmit XCVR pair 2 from FPGA
A9 INT_TX_P3 1.5-V PCML AA41 Transmit XCVR pair 3 from FPGA
B9 INT_TX_N3 1.5-V PCML AA42 Transmit XCVR pair 3 from FPGA
A3 INT_TX_P4 1.5-V PCML AU41 Transmit XCVR pair 4 from FPGA
B3 INT_TX_N4 1.5-V PCML AU42 Transmit XCVR pair 4 from FPGA
D2 INT_TX_P5 1.5-V PCML AY39 Transmit XCVR pair 5 from FPGA
E2 INT_TX_N5 1.5-V PCML AY40 Transmit XCVR pair 5 from FPGA
D4 INT_TX_P6 1.5-V PCML AR41 Transmit XCVR pair 6 from FPGA
E4 INT_TX_N6 1.5-V PCML AR42 Transmit XCVR pair 6 from FPGA
A5 INT_TX_P7 1.5-V PCML AL41 Transmit XCVR pair 7 from FPGA
B5 INT_TX_N7 1.5-V PCML AL42 Transmit XCVR pair 7 from FPGA
G5 INT_TX_P8 1.5-V PCML AN41 Transmit XCVR pair 8 from FPGA
H5 INT_TX_N8 1.5-V PCML AN42 Transmit XCVR pair 8 from FPGA
G3 INT_TX_P9 1.5-V PCML AT39 Transmit XCVR pair 9 from FPGA
H3 INT_TX_N9 1.5-V PCML AT40 Transmit XCVR pair 9 from FPGA
J4 INT_TX_P10 1.5-V PCML AJ41 Transmit XCVR pair 10 from FPGA
K4 INT_TX_N10 1.5-V PCML AJ42 Transmit XCVR pair 10 from FPGA
G1 INT_TX_P11 1.5-V PCML AV39 Transmit XCVR pair 11 from FPGA
H1 INT_TX_N11 1.5-V PCML AV40 Transmit XCVR pair 11 from FPGA
B1 INT_LSB_CON_RX_CLK_N LVDS — Receive clock for the first 12 bits of the bus
A1 INT_LSB_CON_RX_CLK_P LVDS — Receive clock for the first 12 bits of the bus
E10 INT_LSB_CON_RX_FC_CK 2.5-V LVCMOS AJ20
Receive flow control clock signal for the first
12 bits of the bus
H7 INT_LSB_CON_RX_FC_DATA 2.5-V LVCMOS AL35
Receive flow control data signal for the first
12 bits of the bus
H9 INT_LSB_CON_RX_FC_SYNC 2.5-V LVCMOS BD11
Receive flow control synchronization signal
for the first 12 bits of the bus
A7 INT_RX_P0 1.5-V PCML AH43 Receive XCVR pair 0 to FPGA
B7 INT_RX_N0 1.5-V PCML AH44 Receive XCVR pair 0 to FPGA
D6 INT_RX_P1 1.5-V PCML AK43 Receive XCVR pair 1 to FPGA
E6 INT_RX_N1 1.5-V PCML AK44 Receive XCVR pair 1 to FPGA
D8 INT_RX_P2 1.5-V PCML AF43 Receive XCVR pair 2 to FPGA
E8 INT_RX_N2 1.5-V PCML AF44 Receive XCVR pair 2 to FPGA
A9 INT_RX_P3 1.5-V PCML AD43 Receive XCVR pair 3 to FPGA
B9 INT_RX_N3 1.5-V PCML AD44 Receive XCVR pair 3 to FPGA
A3 INT_RX_P4 1.5-V PCML AY43 Receive XCVR pair 4 to FPGA
Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)
Board
Reference
Schematic Signal Name I/O Standard
Stratix V GX
Device Pin
Number
Description