Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 55)

Chapter 2: Board Components 2–47
Components and Interfaces
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
R2 DDR3B_A7 1.5-V SSTL T21 Address bus
T8 DDR3B_A8 1.5-V SSTL K16 Address bus
R3 DDR3B_A9 1.5-V SSTL U21 Address bus
L7 DDR3B_A10 1.5-V SSTL B10 Address bus
R7 DDR3B_A11 1.5-V SSTL N16 Address bus
N7 DDR3B_A12 1.5-V SSTL B13 Address bus
T3 DDR3B_A13 1.5-V SSTL V19 Address bus
M2 DDR3B_BA0 1.5-V SSTL B19 Bank address bus
N8 DDR3B_BA1 1.5-V SSTL G13 Bank address bus
M3 DDR3B_BA2 1.5-V SSTL L20 Bank address bus
K3 DDR3B_CASN 1.5-V SSTL M18 Column address select
K7 DDR3B_CK_N 1.5-V SSTL D9 Clock input N
J7 DDR3B_CK_P 1.5-V SSTL E8 Clock input P
K9 DDR3B_CKE 1.5-V SSTL P20 Clock enable
L2 DDR3B_CSN 1.5-V SSTL D11 Chip select
E3 DDR3B_DQ0 1.5-V SSTL J13 Data bus
F7 DDR3B_DQ1 1.5-V SSTL H13 Data bus
F2 DDR3B_DQ2 1.5-V SSTL F13 Data bus
F8 DDR3B_DQ3 1.5-V SSTL K13 Data bus
H3 DDR3B_DQ4 1.5-V SSTL H15 Data bus
H8 DDR3B_DQ5 1.5-V SSTL H14 Data bus
G2 DDR3B_DQ6 1.5-V SSTL G14 Data bus
H7 DDR3B_DQ7 1.5-V SSTL J16 Data bus
D7 DDR3B_DQ8 1.5-V SSTL W17 Data bus
C3 DDR3B_DQ9 1.5-V SSTL Y17 Data bus
C8 DDR3B_DQ10 1.5-V SSTL R15 Data bus
C2 DDR3B_DQ11 1.5-V SSTL P15 Data bus
A7 DDR3B_DQ12 1.5-V SSTL V13 Data bus
A2 DDR3B_DQ13 1.5-V SSTL W14 Data bus
B8 DDR3B_DQ14 1.5-V SSTL T15 Data bus
A3 DDR3B_DQ15 1.5-V SSTL V15 Data bus
E3 DDR3B_DQ16 1.5-V SSTL L14 Data bus
F7 DDR3B_DQ17 1.5-V SSTL T16 Data bus
F2 DDR3B_DQ18 1.5-V SSTL M15 Data bus
F8 DDR3B_DQ19 1.5-V SSTL K15 Data bus
H3 DDR3B_DQ20 1.5-V SSTL P16 Data bus
H8 DDR3B_DQ21 1.5-V SSTL R16 Data bus
G2 DDR3B_DQ22 1.5-V SSTL J15 Data bus
H7 DDR3B_DQ23 1.5-V SSTL T17 Data bus
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description