Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 53)

Chapter 2: Board Components 2–45
Components and Interfaces
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
Table 2–35 lists the pin assignments for the DDR3 interface and their corresponding
schematic signal names and Stratix V GX pin numbers.
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description
DDR3 Port A Interface (U24, U31)
N3 DDR3A_A0 1.5-V SSTL D10 Address bus
P7 DDR3A_A1 1.5-V SSTL G8 Address bus
P3 DDR3A_A2 1.5-V SSTL M12 Address bus
N2 DDR3A_A3 1.5-V SSTL F9 Address bus
P8 DDR3A_A4 1.5-V SSTL K12 Address bus
P2 DDR3A_A5 1.5-V SSTL H8 Address bus
R8 DDR3A_A6 1.5-V SSTL J9 Address bus
R2 DDR3A_A7 1.5-V SSTL P8 Address bus
T8 DDR3A_A8 1.5-V SSTL B7 Address bus
R3 DDR3A_A9 1.5-V SSTL P12 Address bus
L7 DDR3A_A10 1.5-V SSTL N8 Address bus
R7 DDR3A_A11 1.5-V SSTL K10 Address bus
N7 DDR3A_A12 1.5-V SSTL K9 Address bus
T3 DDR3A_A13 1.5-V SSTL U14 Address bus
M2 DDR3A_BA0 1.5-V SSTL F8 Bank address bus
N8 DDR3A_BA1 1.5-V SSTL L9 Bank address bus
M3 DDR3A_BA2 1.5-V SSTL E9 Bank address bus
K3 DDR3A_CASN 1.5-V SSTL A8 Column address select
K7 DDR3A_CK_N 1.5-V SSTL L8 Clock input N
J7 DDR3A_CK_P 1.5-V SSTL M8 Clock input P
K9 DDR3A_CKE 1.5-V SSTL H12 Clock enable
L2 DDR3A_CSN 1.5-V SSTL M9 Chip select
E3 DDR3A_DQ0 1.5-V SSTL V9 Data bus
F7 DDR3A_DQ1 1.5-V SSTL T11 Data bus
F2 DDR3A_DQ2 1.5-V SSTL T10 Data bus
F8 DDR3A_DQ3 1.5-V SSTL V10 Data bus
H3 DDR3A_DQ4 1.5-V SSTL R12 Data bus
H8 DDR3A_DQ5 1.5-V SSTL T12 Data bus
G2 DDR3A_DQ6 1.5-V SSTL R10 Data bus
H7 DDR3A_DQ7 1.5-V SSTL L12 Data bus
D7 DDR3A_DQ8 1.5-V SSTL J12 Data bus
C3 DDR3A_DQ9 1.5-V SSTL H11 Data bus
C8 DDR3A_DQ10 1.5-V SSTL G10 Data bus
C2 DDR3A_DQ11 1.5-V SSTL F10 Data bus
A7 DDR3A_DQ12 1.5-V SSTL N11 Data bus