Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 47)

Chapter 2: Board Components 2–39
Components and Interfaces
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
86 CFP_RX_N2 1.5-V PCML AK1 Receive XCVR pair 2 to FPGA
88 CFP_RX_P3 1.5-V PCML AH2 Receive XCVR pair 3 to FPGA
89 CFP_RX_N3 1.5-V PCML AH1 Receive XCVR pair 3 to FPGA
91 CFP_RX_P4 1.5-V PCML AD2 Receive XCVR pair 4 to FPGA
92 CFP_RX_N4 1.5-V PCML AD1 Receive XCVR pair 4 to FPGA
94 CFP_RX_P5 1.5-V PCML AB2 Receive XCVR pair 5 to FPGA
95 CFP_RX_N5 1.5-V PCML AB1 Receive XCVR pair 5 to FPGA
97 CFP_RX_P6 1.5-V PCML Y2 Receive XCVR pair 6 to FPGA
98 CFP_RX_N6 1.5-V PCML Y1 Receive XCVR pair 6 to FPGA
100 CFP_RX_P7 1.5-V PCML V2 Receive XCVR pair 7 to FPGA
101 CFP_RX_N7 1.5-V PCML V1 Receive XCVR pair 7 to FPGA
103 CFP_RX_P8 1.5-V PCML T2 Receive XCVR pair 8 to FPGA
104 CFP_RX_N8 1.5-V PCML T1 Receive XCVR pair 8 to FPGA
106 CFP_RX_P9 1.5-V PCML M2 Receive XCVR pair 9 to FPGA
107 CFP_RX_N9 1.5-V PCML M1 Receive XCVR pair 9 to FPGA
48 CFP_T_MDC 2.5-V LVCMOS AN31 Management data clock
47 CFP_T_MDIO 2.5-V LVCMOS AH12 Management data I/O (bi-directional data)
46 CFP_T_PRTADR0 2.5-V LVCMOS — MDIO port address
45 CFP_T_PRTADR1 2.5-V LVCMOS — MDIO port address
44 CFP_T_PRTADR2 2.5-V LVCMOS — MDIO port address
43 CFP_T_PRTADR3 2.5-V LVCMOS — MDIO port address
42 CFP_T_PRTADR4 2.5-V LVCMOS — MDIO port address
36 CFP_TX_DIS 2.5-V LVCMOS BC11 Transmitter disable
24 CFP_TX_MCLK_N CML — Only used for optical waveform testing.
25 CFP_TX_MCLK_P CML — Only used for optical waveform testing.
113 CFP_TX_P0 1.5-V PCML AL4 Transmit XCVR pair 0 from FPGA
114 CFP_TX_N0 1.5-V PCML AL3 Transmit XCVR pair 0 from FPGA
116 CFP_TX_P1 1.5-V PCML AJ4 Transmit XCVR pair 1 from FPGA
117 CFP_TX_N1 1.5-V PCML AJ3 Transmit XCVR pair 1 from FPGA
119 CFP_TX_P2 1.5-V PCML AG4 Transmit XCVR pair 2 from FPGA
120 CFP_TX_N2 1.5-V PCML AG3 Transmit XCVR pair 2 from FPGA
122 CFP_TX_P3 1.5-V PCML AE4 Transmit XCVR pair 3 from FPGA
123 CFP_TX_N3 1.5-V PCML AE3 Transmit XCVR pair 3 from FPGA
125 CFP_TX_P4 1.5-V PCML AA4 Transmit XCVR pair 4 from FPGA
126 CFP_TX_N4 1.5-V PCML AA3 Transmit XCVR pair 4 from FPGA
128 CFP_TX_P5 1.5-V PCML W4 Transmit XCVR pair 5 from FPGA
129 CFP_TX_N5 1.5-V PCML W3 Transmit XCVR pair 5 from FPGA
131 CFP_TX_P6 1.5-V PCML U4 Transmit XCVR pair 6 from FPGA
Table 2–31. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
(J25)
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin
Number
Description