Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 26)

2–18 Chapter 2: Board Components
Configuration, Status, and Setup Elements
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
FPGA Programming from Flash Memory
On either power-up or by pressing the LOAD or FACTORY push button (S5 or S6), the
MAX II CPLD System Controller’s parallel flash loader configures the FPGA from the
flash memory. The configuration program select push-button, PGM_SEL, (S8) selects
between two .pof files (factory or user) stored in the flash. The MAX II CPLD System
Controller uses the Altera Parallel Flash Loader (PFL) megafunction to configure the
FPGA by reading data from the flash and converting it to FPP format. This data is
then written to the FPGA’s dedicated configuration pins during configuration.
Figure 2–4 shows the block diagram for the MAX II+Flash FPP configuration.
Additionally, ten green configuration status LEDs (D24–D29 and D31–D34) indicate
the FPP configuration status. After configuration completes, you can determine which
.pof
image is loaded into the FPGA by observing the FACTORY_POF LED (D31) or the
USER1_POF , USER2_POF, USER3_POF LEDs (D34, D33, D32).
f
For more information on the flash map storage, refer to the 100G Development Kit,
Stratix V GX Edition User Guide .
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
using an external USB-Blaster device with the Quartus II Programmer running on a
PC. The MAX II JTAG configuration jumper allows you to remove the MAX II CPLD
from the JTAG chain so that the FPGA is the only device on the chain.
Figure 2–4. MAX II+Flash FPP Configuration
LOAD/FACTORY
Push Button
PGM_SEL
Push Button
MAX II
CPLD
FPP Configuration
Flash
Flash
Flash
Memory
FA
CT
OR
Y_POF LED
USER_POF LED
MAX_ERR
OR LED
Stratix V GX
FPGA