Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 50)

2–42 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
B3 INT_RX_N4 1.5-V PCML AY44 Receive XCVR pair 4 to FPGA
D2 INT_RX_P5 1.5-V PCML BB43 Receive XCVR pair 5 to FPGA
E2 INT_RX_N5 1.5-V PCML BB44 Receive XCVR pair 5 to FPGA
D4 INT_RX_P6 1.5-V PCML AV43 Receive XCVR pair 6 to FPGA
E4 INT_RX_N6 1.5-V PCML AV44 Receive XCVR pair 6 to FPGA
A5 INT_RX_P7 1.5-V PCML AP43 Receive XCVR pair 7 to FPGA
B5 INT_RX_N7 1.5-V PCML AP44 Receive XCVR pair 7 to FPGA
G5 INT_RX_P8 1.5-V PCML AT43 Receive XCVR pair 8 to FPGA
H5 INT_RX_N8 1.5-V PCML AT44 Receive XCVR pair 8 to FPGA
G3 INT_RX_P9 1.5-V PCML AW41 Receive XCVR pair 9 to FPGA
H3 INT_RX_N9 1.5-V PCML AW42 Receive XCVR pair 9 to FPGA
J4 INT_RX_P10 1.5-V PCML AM43 Receive XCVR pair 10 to FPGA
K4 INT_RX_N10 1.5-V PCML AM44 Receive XCVR pair 10 to FPGA
G1 INT_RX_P11 1.5-V PCML BA41 Receive XCVR pair 11 to FPGA
H1 INT_RX_N11 1.5-V PCML BA42 Receive XCVR pair 11 to FPGA
Interlaken Interface Channel 12-23 (J38, J60)
B1 INT_MSB_CON_TX_CLK_N LVDS —
Transmit clock for the second 12 bits of the
bus
A1 INT_MSB_CON_TX_CLK_P LVDS —
Transmit clock for the second 12 bits of the
bus
E10 INT_MSB_CON_TX_FC_CK 2.5-V LVCMOS AK33
Transmit flow control clock signal for the
second 12 bits of the bus
H7 INT_MSB_CON_TX_FC_DATA 2.5-V LVCMOS AE36
Transmit flow control data signal for the
second 12 bits of the bus
H9 INT_MSB_CON_TX_FC_SYNC 2.5-V LVCMOS AH21
Transmit flow control synchronization signal
for the second 2 bits of the bus
A7 INT_TX_P12 1.5-V PCML F39 Transmit XCVR pair 12 from FPGA
B7 INT_TX_N12 1.5-V PCML F40 Transmit XCVR pair 12 from FPGA
D6 INT_TX_P13 1.5-V PCML G41 Transmit XCVR pair 13 from FPGA
E6 INT_TX_N13 1.5-V PCML G42 Transmit XCVR pair 13 from FPGA
D8 INT_TX_P14 1.5-V PCML E41 Transmit XCVR pair 14 from FPGA
E8 INT_TX_N14 1.5-V PCML E42 Transmit XCVR pair 14 from FPGA
A9 INT_TX_P15 1.5-V PCML D39 Transmit XCVR pair 15 from FPGA
B9 INT_TX_N15 1.5-V PCML D40 Transmit XCVR pair 15 from FPGA
A3 INT_TX_P16 1.5-V PCML R41 Transmit XCVR pair 16 from FPGA
B3 INT_TX_N16 1.5-V PCML R42 Transmit XCVR pair 16 from FPGA
D2 INT_TX_P17 1.5-V PCML W41 Transmit XCVR pair 17 from FPGA
E2 INT_TX_N17 1.5-V PCML W42 Transmit XCVR pair 17 from FPGA
D4 INT_TX_P18 1.5-V PCML L41 Transmit XCVR pair 18 from FPGA
Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board
Reference
Schematic Signal Name I/O Standard
Stratix V GX
Device Pin
Number
Description