Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 56)

2–48 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
D7 DDR3B_DQ24 1.5-V SSTL C16 Data bus
C3 DDR3B_DQ25 1.5-V SSTL C15 Data bus
C8 DDR3B_DQ26 1.5-V SSTL F14 Data bus
C2 DDR3B_DQ27 1.5-V SSTL E14 Data bus
A7 DDR3B_DQ28 1.5-V SSTL C13 Data bus
A2 DDR3B_DQ29 1.5-V SSTL A13 Data bus
B8 DDR3B_DQ30 1.5-V SSTL A14 Data bus
A3 DDR3B_DQ31 1.5-V SSTL D14 Data bus
F3 DDR3B_DQS_P0 1.5-V SSTL L15 Data strobe P byte lane 0
G3 DDR3B_DQS_N0 1.5-V SSTL K14 Data strobe N byte lane 0
C7 DDR3B_DQS_P1 1.5-V SSTL Y16 Data strobe P byte lane 1
B7 DDR3B_DQS_N1 1.5-V SSTL W16 Data strobe N byte lane 1
F3 DDR3B_DQS_P2 1.5-V SSTL V17 Data strobe P byte lane 2
G3 DDR3B_DQS_N2 1.5-V SSTL U17 Data strobe N byte lane 2
C7 DDR3B_DQS_P3 1.5-V SSTL E15 Data strobe P byte lane 3
B7 DDR3B_DQS_N3 1.5-V SSTL D15 Data strobe N byte lane 3
K1 DDR3B_ODT 1.5-V SSTL U12 On-die termination
J3 DDR3B_RASN 1.5-V SSTL B17 Row address select
T2 DDR3B_RSTN 1.5-V SSTL V16 Reset
L3 DDR3B_WEN 1.5-V SSTL K18 Write enable
DDR3 Port C Interface (U26, U33)
N3 DDR3C_A0 1.5-V SSTL D21 Address bus
P7 DDR3C_A1 1.5-V SSTL L21 Address bus
P3 DDR3C_A2 1.5-V SSTL J22 Address bus
N2 DDR3C_A3 1.5-V SSTL G22 Address bus
P8 DDR3C_A4 1.5-V SSTL H21 Address bus
P2 DDR3C_A5 1.5-V SSTL M22 Address bus
R8 DDR3C_A6 1.5-V SSTL K20 Address bus
R2 DDR3C_A7 1.5-V SSTL J21 Address bus
T8 DDR3C_A8 1.5-V SSTL H20 Address bus
R3 DDR3C_A9 1.5-V SSTL K21 Address bus
L7 DDR3C_A10 1.5-V SSTL T22 Address bus
R7 DDR3C_A11 1.5-V SSTL G20 Address bus
N7 DDR3C_A12 1.5-V SSTL N22 Address bus
T3 DDR3C_A13 1.5-V SSTL K22 Address bus
M2 DDR3C_BA0 1.5-V SSTL E21 Bank address bus
N8 DDR3C_BA1 1.5-V SSTL P21 Bank address bus
M3 DDR3C_BA2 1.5-V SSTL D20 Bank address bus
K3 DDR3C_CASN 1.5-V SSTL F20 Column address select
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description