Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 74)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 74
SystemVerilog Tutorials
Verifying a Master DUT
April 2014
Example 6-7. Transfer Receiving
// Packet receiving
forever
begin
trans = bfm.create_slave_transaction();
i = 0;
last = 0;
while(!last)
begin
if(m_insert_wait)
begin
ready_delay();
end
bfm.get_transfer(trans, i, last);
++i;
end
end
end