Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 194)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 194
Getting Started with Qsys and the BFMs
Setting Up Simulation from the Windows GUI
April 2014
Figure 12-5. Quartus II Software Displays the Connectivity of the Example
Note
If you are using VHDL, you must select each BFM and verify that the index number
specified for the BFM is correct. An information dialog displays the properties of the
BFM when you select it. Ensure the specified BFM index is correct in this dialog. If you
do not know the correct index number, check the VHDL code for the BFM.
4. Click the Generate drop-down menu on the Qsys toolbar, and select Generate HDL to
open the Generation options window, as shown in Figure 12-5 .
5. Specify the Generation window options shown in the following:
a. Synthesis section
i. Set the Create HDL design files for synthesis to None to inhibit the generation of
synthesis files.
ii. Uncheck the Create block symbol file (.bsf) check box.
b. Simulation section
i. Set the Create simulation model to Verilog.
c. Change the path of the example. In the Path field of the Output Directory section,
ensure the path correctly specifies the subdirectory ex1_back_to_back_sv, which is
the subdirectory containing the example that you just copied into a temporary
directory.
Note
If the subdirectory name of the example is duplicated in the Path field, you must remove
one of the duplicated subdirectory names. To reset the path, double-click the square
browse button to the right of the Path field and locate the correct path of the example.