Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 43)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 43
April 2014
Chapter 4
SystemVerilog Slave BFM
This section provides information about the SystemVerilog slave BFM. It has an API that
contains tasks and functions to configure the BFM and to access the dynamic
Transaction
Record during the lifetime of a transaction.
Slave BFM Protocol Support
The slave BFM supports the full AMBA AXI4-Stream protocol.
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA
AXI4-Stream Protocol Specification chapter, which you can reference for details of the
following slave BFM API timing and events.
The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period
with signal events sampled and driven at rising ACLK edges. Therefore, the slave BFM does
not contain any timescale, timeunit, or timeprecision declarations with the signal setup and hold
times specified in units of simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the test
bench and design IP as a result of these directives, declarations, options, or initialization files:
•
` timescale directives in design elements
•
Timeprecision declarations in design elements
•
Compiler command-line options
•
Simulation command-line options
•
Local or site-wide simulator initialization files
If there is no timescale directive, the default time unit and time precision are tool specific. The
recommended practice is to use timeunit and timeprecision declarations. Refer to the IEEE
Standard for SystemVerilog, Section 3.14, for details.