Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 159)

VHDL Monitor BFM
Monitor Assertions
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 159
April 2014
1.
Refer to Monitor Timing and Events for details of simulator time-steps.
Monitor Assertions
The monitor BFM performs protocol error checking using built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
AXI4STREAM_CONFIG_HOLD_TIME The hold-time after the active
edge of ACLK, in units of
simulator time-steps for all
signals.
1
Default: 0.
AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles.
Default: 10000.
AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_
ASSERTION_TO_TREADY The maximum delay permitted
between the assertion of TVALID
to the assertion of TREADY.
Default: 10000.
Master Attributes
AXI4STREAM_LAST_DURING_IDLE Controls the value of TLAST
during idle.
0 = TLAST driven to 0 during
idle (default)
1 = TLAST driven to 1 during
idle
Error Detection
AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all
assertion checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4STREAM_CONFIG_ENABLE_ASSERTION Individual enable/disable of an
assertion check in the BFM.
Refer to
Assertions chapter for
details
0 = disabled
1 = enabled (default)
Table 10-2. Monitor BFM Configuration (cont.)
Configuration Field Description