Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 209)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 209
April 2014
Appendix A
SystemVerilog Master and Slave Test
Programs
SystemVerilog Master Test Program
The example code in this section is a simplified AXI4-Stream master that illustrates how you
can use the mgc_axi4stream_master BFM.
//
*************************************************************************
****
//
// Copyright 2007-2013 Mentor Graphics Corporation
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
TERMS.
//
//
*************************************************************************
****
/*
This is a simple example of an axi4stream master to demonstrate the
mgc_axi4stream_master BFM usage.
This master performs a directed test, initiating 10 sequential packets
at higher abstraction level
followed by 10 transfer at phase level.
*/
import mgc_axi4stream_pkg::*;
module master_test_program #(int AXI4_ID_WIDTH = 18, int AXI4_USER_WIDTH =
8, int AXI4_DEST_WIDTH = 18, int AXI4_DATA_WIDTH = 1024)
(
mgc_axi4stream_master bfm
);
initial
begin
axi4stream_transaction trans;
static int byte_count = AXI4_DATA_WIDTH/8;
int transfer_count;
bit last;
/*******************
** Initialisation **