Altera LVDS SERDES - Manual (Page 8)

Signals
The following tables list the input and output signals for the Altera LVDS SERDES IP core.
N represents the LVDS interface width and the number of serial channels while J represents the
SERDES factor of the interface. Note:
Table 2: Common TX and RX Signals
Description Type Direction Width Signal Name
PLL reference clock. Clock Input 1
inclock
Active-high asynchronous reset to all blocks
in Altera LVDS SERDES and PLL. Reset Input 1
pll_areset
Asserted when internal PLL is locked. Control Output 1
pll_locked
Table 3: RX Signals
Description Type Direction Width Signal Name
LVDS serial input data. Data Input N
rx_in
Asynchronous, active-high reset to the clock-
data alignment circuitry (bitslip). Reset Input N
rx_bitslip_reset
Positive-edge triggered increment for bitslip
circuitry. Each assertion adds one bit of
latency to the received bitstream. Control Input N
rx_bitslip_ctrl
Asynchronous, active-high signal prevents
the DPA circuitry from switching to a new
clock phase on the target channel. When held
high, the selected channel(s) hold their
current phase setting. When held low, the
DPA block on selected channel(s) monitors
the phase of the incoming data stream
continuously and selects a new clock phase
when needed. Applicable in DPA-FIFO and
soft-CDR modes only. Control Input N
rx_dpa_hold
Asynchronous, active-high reset to DPA
blocks. Minimum pulse width is one parallel
clock period. Applicable in DPA-FIFO and
soft-CDR modes only. Reset Input N
rx_dpa_reset
Asynchronous, active-high reset to FIFO
block. Minimum pulse width is one parallel
clock period. Applicable in DPA-FIFO mode
only. Reset Input N
rx_fifo_reset
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Signals 8
2014.08.18