Altera LVDS SERDES - Manual (Page 17)

Specifying phase shift values greater than 360° will change the MSB location within the parallel data.
By default, the MSB from the serial data will not be the MSB on the parallel data. You can use bitslip
to set the proper word boundary on the parallel data. Refer to
Aligning the Word Boundaries for
more details.
Note:
To specify a center aligned inclock to
rx_in
relationship ( Figure 5 ), enter a phase shift value of 180° for the
Desired receiver inclock phase shift (degrees) parameter.
Figure 5: 180° Center Aligned inclock x8 Deserializer Waveform With Single Rate Clock
The phase shift value you enter to specify the inclock to rx_in relationship is independent of the inclock
frequency. To specify a center aligned DDR inclock to
rx_in
relationship ( Figure 6 ), enter a phase shift
value of 180° for the Desired receiver inclock phase shift (degrees) parameter.
Figure 6: 180° Center Aligned inclock x8 Deserializer Waveform With DDR Clock
Setting the Transmitter Output Clock Parameters
The
tx_outclock
relationship to the
tx_out
data is specified with two parameters:
• Desired tx_outclock phase shift (degrees)
• Tx_outclock division factor
These parameters set the phase and frequency of the
tx_outclock
based on the
fclk
which operates at the
serial data rate. You can specify the desired tx_outclock phase shift relative to the tx_out data at 45°
increments of the
fclk
. You can set the
tx_outclock
frequency using the available division factors from
the drop-down list.
Use 0° to specify the tx_outclock phase to be rising edge aligned to the MSB of the serial data on tx_out
( Figure 7 ).
Altera Corporation Altera LVDS SERDES IP Core User Guide
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17 Setting the Transmitter Output Clock Parameters
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2014.08.18