Altera LVDS SERDES - Manual (Page 23)

Obtaining TCCS Report
For LVDS transmitters, the TimeQuest Timing Analyzer provides a TCCS report, which shows TCCS values
for serial output ports.
To obtain the TCCS report (
report_tccs
), follow these steps:
1. In the Quartus II software, under the Tools menu, click TimeQuest Timing Analyzer.
2. From the TimeQuest Timing Analyzer, under Reports, select Device Specific and click Report TCCS
Timing Analysis in FPGA
The Altera LVDS SERDES IP core generation creates the clock settings of the SERDES hardware and the
core clock for a successful timing analysis of the IP core.
Table 8: Clock for the TX, Non-DPA RX, and DPA-FIFO RX Mode
This table lists the clock for TX, non-DPA RX, and DPA-FIFO RX modes. Because the frequency of LVDS fast clock
is higher than the user core clock by the serialization factor, the IP generation also creates multicycle path constraints
for proper timing analysis at the SERDES - core interface.
Description Clock
_*_outclk[*]
Core clock
_*_lvds_clk[*]
LVDS fast clock
Table 9: Clock for Soft-CDR RX Mode
This table lists the clock for soft-CDR RX mode.
Description Clock
_core_ck_name_
Core clock
_dpa_ck_name_
DPA fast clock
To ensure proper timing analysis, instead of multicycle constraints, the IP core generation creates clock
settings at
rx_out in the format of _core_data_out__ for
rising edge data and
_core_data_out___neg
for falling edge
data.
With these proper clock settings, the TimeQuest Timing Analyzer will timing analyze the LVDS SERDES -
Core interface transfer and the within core transfer correctly.
External PLL Mode
When you enable the Use external PLL parameter in the PLL Settings tab, the IP generation does not create
clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.
However, because some of the SERDES constraints derived from the PLL clocks, those PLL clock settings
must already be created when the .sdc of the Altera LVDS SERDES is being read. To ensure that the .sdc
has the PLL clock settings was read before the one for LVDS SERDES, ensure that the .sdc of the PLL appears
before the LVDS SERDES .qip in the .qsf of your project.
Altera Corporation Altera LVDS SERDES IP Core User Guide
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23 Obtaining TCCS Report
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2014.08.18