Altera LVDS SERDES - Manual (Page 5)

DPA FIFO
In DPA-FIFO mode, the DPA FIFO synchronizes the retimed data to the high-speed LVDS clock domain.
Because the DPA clock may shift phase during the initial lock period, the FIFO must be held in reset state
until the DPA locks; otherwise, there may be a data run-through condition due to the FIFO write pointer
creeping up to the read pointer.
Bitslip
Use bitslip circuitry to insert latencies in increments of one fclk cycle for data word alignment. The data
slips one bit for every pulse of the
rx_bitslip_ctrl
signal. You must wait at least five core clock cycles
before checking if the data is aligned because it will take at least two core clock cycles to purge the undefined
data.
When enough bitslip signals are sent to rollover the bitslip counter, the
rx_bitslip_max
status signal is
asserted after five core clock cycles to indicate that it has reached its maximum counter value of the bitslip
counter rollover point.
Deserializer
The deserializer consists of shift registers. The deserialization factor determines the depth of the shift registers.
The
loaden
signal is a pulse with a frequency of the
fclk
divided by the deserialization factor. The
deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.
Figure 3: LVDS x8 Deserializer Waveform
7 6 5 4 3 2 1 0 a b c d e f g h A B C D E F G H X X X X X X X X
ABCDEFGH abcdefgh 76543210 XXXXXXXX
RX_IN
FCLK
LOADEN
RX_OUT[7:0]
Description Signal
LVDS data stream, input to the Altera LVDS SERDES channel. rx_in
Clock used for receiver.
fclk
Enable signal for deserialization. loaden
Deserialized data.
rx_out[7:0]
Initialization and Reset
This section describes the initialization and reset aspects, using control characters. This section also provides
a recommended initialization and reset flow for the Altera LVDS SERDES IP core.
Altera Corporation Altera LVDS SERDES IP Core User Guide
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5 DPA FIFO
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2014.08.18