Altera LVDS SERDES - Manual (Page 6)

Initializing the Altera LVDS SERDES IP Core
With the Altera LVDS SERDES IP core, the PLL must be locked to the reference clock prior to using the
SERDES blocks for data transfer. The PLL starts to lock to the reference clock during device initialization.
The PLL is operational when the PLL achieves lock during user mode. If the clock reference is not stable
during device initialization, the PLL output clock phase shifts becomes corrupted.
When the PLL output clock phase shifts are not set correctly, the data transfer between the high-speed LVDS
domain and the low-speed parallel domain might not be successful, which leads to data corruption. Assert
the
pll_areset
port for at least 10 ns, and then deassert the
pll_areset
port and wait until the PLL lock
becomes stable. After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
When using DPA, further steps are required for initialization and reset recovery. The DPA circuit samples
the incoming data and finds the optimal phase tap from the PLL to capture data on a receiver channel-by-
channel basis. If the PLL has not locked to a stable clock source, the DPA circuit might lock prematurely to
a non-ideal phase tap. Use the
rx_dpa_reset
port to keep the DPA in reset until the PLL lock signal is
asserted and stable.
The rx_dpa_locked signal asserts when the DPA has found the optimal phase tap.
Altera recommends asserting the
rx_fifo_reset
port after the
rx_dpa_locked
signal asserts, and
then deassert the
rx_fifo_reset
port to begin receiving data.
Note:
Each time the DPA shifts the phase taps during normal operation to track variations between the relationship
of the reference clock source and the data, the timing margin for the data transfer between clock domains
is reduced.
The Altera LVDS SERDES IP core asserts the rx_dpa_locked port upon initial DPA lock. When you enable
the Enable DPA loss of lock on one change option, the
rx_dpa_locked
port deasserts after one change in
phase. If this option is disabled, the
rx_dpa_locked
signal will deassert after two phase changes in the same
direction.
Altera recommends using the data checkers to ensure data accuracy. Note:
Resetting the DPA
When the data becomes corrupted, you must reset the DPA circuitry using the rx_dpa_reset port and
rx_fifo_reset
port.
Assert the rx_dpa_reset port to reset the entire DPA block. This requires the DPA to be trained before it
is ready for data capture.
Altera recommends toggling the
rx_fifo_reset
port after
rx_dpa_locked
is asserted. This ensures
the synchronization FIFO is set with the optimal timing to transfer data between the DPA and high-
speed LVDS clock domains.
Note:
Assert the
rx_fifo_reset
port to reset only the synchronization FIFO. This allows you to continue system
operation without having to re-train the DPA. Using this port can fix data corruption because it resets the
FIFO; however, it does not reset the DPA circuit.
When the DPA is locked, the Altera LVDS SERDES block is ready to capture data. The DPA finds the optimal
sample location to capture each bit. The next step is to set up the word boundary using custom logic to
control the
rx_bitslip_ctrl port on a channel-by-channel basis.
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Initializing the Altera LVDS SERDES IP Core 6
2014.08.18