Altera LVDS SERDES - Manual (Page 15)

Description Value Parameter
Specifies the closest achievable receiver inclock
phase shift to the desired receiver inclock phase
shift. Legal values are
dependent on the
fclk and inclock
frequencies.
Refer to
Setting
the Receiver
Input Clock
Parameters
on
page 16.
Actual receiver inclock phase shift
(degrees)
Transmitter Settings Tab
Description Value Parameter
Allows you to either clock the core registers with
the tx_coreclock or the PLL refclk. If you select
inclock, the refclk frequency must be equal to the
data rate divided by the serialization factor.
This parameter is available in TX functional mode
only.
tx_coreclock or
inclock
TX core registers clock
When enabled, the IP core exposes the
tx_
coreclock
port which you can use to drive the core
logic feeding the transmitter.
—
Enable tx_coreclock port
When enabled, the IP core exposes the
tx_
outclock port. The frequency of the tx_outclock
port is dependent on the setting for the tx_outclock
division factor parameter. The phase of the
tx_
outclock port is dependent on the Desired tx_
outclock phase shift parameter. This parameter
takes up an additional channel, which reduces the
max number of channels per TX interface by 1
—
Enable tx_outclock port
Allows you to specify the phase relationship
between the outclock and outgoing serial data in
degrees of the LVDS fast clock. Refer to the
Setting the
Transmitter
Output Clock
Parameters
on
page 17.
Desired tx_outclock phase shift
(degrees)
Altera Corporation Altera LVDS SERDES IP Core User Guide
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15 Transmitter Settings Tab
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2014.08.18