Altera LVDS SERDES - Manual (Page 2)

Description Functional Mode
In this mode, you must ensure the correct clock-data alignment, as the
incoming data is captured at the bitslip with the
fclk
signal. The DPA and
DPA-FIFO are bypassed. As in the transmitter mode, the fclk signal is
provided by a PLL.
RX Non-DPA Mode
In this mode, the DPA block selects an optimal phase to sample incoming
data from a set of eight DPA clocks running at the
fclk
frequency, each 45°
out of phase. The DPA-FIFO, a circular buffer, samples the incoming data
with the selected DPA clock and forwards the data to LVDS clock domain.
The data released from the DPA-FIFO is then sampled at the bitslip circuitry,
where it is lagged, and thus, realigned to match the desired word boundary
when it is deserialized.
To avoid clock metastability issues, after FIFO resets, wait for two core clock
cycles before resetting the bitslip.
All RX channels must be placed in one I/O bank, which supports
up to 24 channels only. Note:
RX DPA-FIFO
In this mode, the optimal DPA clock (DPACLK) is forwarded into the LVDS
clock domain, where it is used as the
fclk
signal. The local clock generator
produces
rx_divfwdclk
which will be forwarded to the core through a
PCLK network. Note, there is a limitation of the number of soft-CDR
channels due to PCLK usage.
RX interfaces must be placed in one I/O bank, and each bank
only has 12 PCLK resources, hence 12 soft-CDR channels. Note:
For actual soft-CDR supported channel, refer to the respective
device pin out list. Under "Dedicated Tx/Rx Channel", there will
be a value of form
LVDS__
.
The pin pair supports soft-CDR mode only when
is an even number.
Note:
RX Soft-CDR Mode
Functional Description
A single Altera LVDS SERDES channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a
high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. You can configure
the Altera LVDS SERDES channel as a receiver or a transmitter for a single differential I/O. Therefore, an
n-channel LVDS interface contains n-serdes_dpa blocks. The I/O PLLs drive the LVDS clock tree, providing
clocking signals to the Altera LVDS SERDES channel in the I/O bank.
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Functional Description 2
2014.08.18