Altera LVDS SERDES - Manual (Page 3)

Figure 1: Altera LVDS SERDES Channel Diagram
DIN DOUT
DOUT DIN DOUT DIN
DOUT DIN
Clock
Multiplexer
3 lvds_loaden
lvds_fclk
rx_coreclock
IOPLL
8 Serial LVDS
Clock Phases
3
dpa_loaden
dpa_fclk
rx_divfwdclk
10
rx_divfwdclk
rx_coreclock
FPGA
Fabric
LVDS Clock Domain
DPA Clock Domain
+
-
+
-
DPA Circuitry
Retimed
Data DIN
DPA Clock
rx_inclock/tx_inclock
tx_out
Serializer
lvds_fclk dpa_fclk
fclk
loaden
fclk
2
Deserializer Bitslip
LVDS Receiver
rx_in
3
lvds_loaden
lvds_fclk
tx_coreclock
10
LVDS Transmitter
tx_in
tx_coreclock
rx_out
DPA FIFO
(Local Clock Generator)
Each Altera LVDS SERDES channel can be broken down into the following paths, with seven functional
units:
Clock Domain Modes Block Path
LVDS TX mode Serializer TX Data Path
Altera Corporation Altera LVDS SERDES IP Core User Guide
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3 Functional Description
ug_altera_lvds
2014.08.18