Altera LVDS SERDES - Manual (Page 27)

Document Revision History
Table 11: Document Revision History
Changes Version Date
• Clarified that you must wait five core clock cycles before checking
if the data is aligned for bitslip circuitry.
• Changed the
rx_out[9:0]
signal to
rx_out[7:0]
for the
deserializer.
• Clarified that if one of the pins is taken for the refclk , then the
value is 1 to 71 for TX and 1 to 23 for RX. This change is
implemented for the Number of channels parameter.
• Clarified that if one of the pins is taken for the tx_outclock ,
then the value is 1 to 71 for TX. This change is implemented for
the Number of channels parameter.
• Added a new parameter (Use backwards-compatible port
names).
• The Use external PLL is supported in the 14.0a10 release. The
Clock Resource Summary tab guides you to configure your
external PLL.
• Removed the Enable pll_locked port and Enable rx_dpa_locked
port parameters.
• Added the external PLL signals.
• Added timing information.
2014.08.18 August, 2014
Initial release. 2013.11.29 November, 2013
Altera Corporation Altera LVDS SERDES IP Core User Guide
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27 Document Revision History
ug_altera_lvds
2014.08.18