Altera LVDS SERDES - Manual (Page 7)

The bitslip circuit can be reset using the
rx_bitslip_reset
port. This circuit can be reset anytime and is
not dependent on the PLL or DPA circuit operation.
Aligning the Word Boundaries
To align the word boundaries, it is useful to have control characters in the data stream so that your logic can
have a known pattern to search for. You can compare the data received for each channel, compare to the
control character you are looking for, then pulse the
rx_bitslip_ctrl port as required until you successfully
receive the control character.
Altera recommends setting the bitslip rollover count to the deserialization factor or higher, which
allows enough depth in the bitslip circuit to roll through an entire word if required. Note:
If you do not have control characters in the received data, you need a deterministic relationship between
the reference clock and data to predict the word boundary using timing simulation or laboratory measure-
ments. This applies only for non-DPA mode. The only way to ensure a deterministic relationship on the
default word position in the SERDES when the device powers up, or anytime the PLL is reset, is to have a
reference clock equal to the data rate divided by the deserialization factor. For example, if the data rate is
800 Mbps, and the deserialization factor is 8, the PLL requires a 100-MHz reference clock. This is important
because the PLL locks to the rising edge of the reference clock. If you have one rising edge on the reference
clock per serial word received, the deserializer always starts at the same position. Using timing simulation,
or lab measurements, monitor the parallel words received and determine how many pulses are required on
the
rx_bitslip_ctrl
port to set your word boundaries. You can create a simple state machine to apply the
required number of pulses when you enter user mode, or anytime you reset the PLL.
When using DPA or soft-CDR modes, the word boundary is not deterministic. The initial training
of the DPA allows it to move forward or backward in phase relative to the incoming serial data. Thus, Note:
there can be a ± 1-bit of variance in the serial bit where the DPA initially locks. If there are no training
patterns or control characters available in the serial bit stream to use for word alignment, Altera
recommends using non-DPA mode.
Recommended Initialization and Reset Flow
Altera recommends that you follow these steps to initialize and reset the Altera LVDS SERDES IP core:
1. During entry into user mode, or anytime in user mode operation when the interface requires a reset,
assert the
pll_areset
and
rx_dpa_reset
ports.
2. Deassert the pll_areset port and monitor the pll_locked port. For non-DPA mode, skip to step 7 .
3. Deassert the rx_dpa_reset port after the pll_locked port becomes asserted and stable.
4. Apply the DPA training pattern and allow the DPA circuit to lock. (If a training pattern is not available,
any data with transitions is required to allow the DPA to lock.) Refer to the respective device data sheet
for DPA lock time specifications.
5. Wait for the rx_dpa_locked port to assert.
6. Assert rx_fifo_reset for at least one parallel clock cycle, and then de-assert rx_fifo_reset .
7. Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the
rx_bitslip_reset
port.
8. Begin word alignment by applying pulses as required to the
rx_bitslip_ctrl
port.
9. When the word boundaries are established on each channel, the interface is ready for operation.
Altera Corporation Altera LVDS SERDES IP Core User Guide
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7 Aligning the Word Boundaries
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2014.08.18