Altera LVDS SERDES - Manual (Page 26)

6. Replace your ALTLVDS_TX or ALTLVDS_RX IP core instantiation in RTL with the Altera LVDS SERDES
IP core.
The Altera LVDS SERDES IP core port names may not match the ALTLVDS_TX or ALTLVDS_RX
IP core port names, so simply changing the IP core name in the instantiation may not be sufficient. Note:
Comparison with Stratix V Devices
The Altera LVDS SERDES IP core has similar features to the Stratix V SERDES feature. The key difference
is the clock network and the ubiquitous RX and TX resource in LVDS I/O banks.
Table 10: Arria 10 and Stratix V Devices Feature Comparison
Stratix V Devices Arria 10 Devices Features
150 MHz - 1.6 GHz Operation Frequency Range
3 to 10 Serialization/Deserialization
Factors
Supported Regular DPA and non-DPA
mode
Supported Clock Forwarding for Soft-
CDR
Every two I/O pairs on every side without HSSI
transceivers
Every I/O pair
(Every two I/O pairs for CDR)
RX Resource
Every two I/O pairs every side without HSSI
transceivers
Every I/O pair TX Resource
RX and TX channels placed on one edge can be
driven by the corner or center PLL.
TX channels can span three
adjacent banks, driven by the
IOPLL in the middle bank.
RX channels are driven by the
IOPLL in the same bank.
PLL Resource
8 Number of DPA Clock Phase
True LVDS, pseudo-differential output True LVDS I/O Standard
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Comparison with Stratix V Devices 26
2014.08.18