Altera LVDS SERDES - Manual (Page 4)

Clock Domain Modes Block Path
DPA DPA FIFO and Soft-
CDR modes DPA Circuitry
RX Data Path
LVDS-DPA domain crossing DPA-FIFO mode DPA FIFO
LVDS Non-DPA and DPA-
FIFO modes
Bitslip and
Deserializer
DPA clock domain Soft CDR modes
Generates PCLK and
LOADEN in these modes Soft-CDR mode Local Clock
Generator
Clock Generation and
Multiplexers
Selects LVDS clock sources for
all modes All modes SERDES Clock
Multiplexers
Serializer
The serializer consists of two sets of registers. The first set of registers captures the parallel data from the
core using the LVDS fast clock. The
loaden
clock is provided alongside the LVDS fast clock, to enable these
capture registers once per coreclock period. After the data is captured, the data is then loaded into a shift
register, which shifts the LSB towards the MSB, one bit per fast clock cycle. The MSB of the shift register
feeds the LVDS output buffer; hence, higher order bits precede lower order bits in the output bitstream.
The following figure shows the serializer waveform.
Figure 2: LVDS x8 Serializer Waveform
7 6 5 4 3 2 1 0 a b c d e f g h A B C D E F X X X X X X X X X X
ABCDEFGH abcdefgh 76543210 XXXXXXXX TXDAT[7:0]
FCLK
LOADEN
LVDSOUT
This waveform is specific to serialization factor = 8.
Description Signal
Data to be serialized (supported serialization factors are 3 -10). txdat[7:0]
Clock used for transmitter. fclk
Enable signal for serialization.
loaden
LVDS data stream, output from the Altera LVDS SERDES channel.
lvdsout
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Serializer 4
2014.08.18