Altera LVDS SERDES - Manual (Page 18)

Figure 7: 0° Edge Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8
Use 180° to specify the
tx_outclock
phase to center aligned to the MSB of the serial data on
tx_out
( Figure
8 ).
Figure 8: 180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8
Phase shift values of 0° through 315° will position the rising edge of the tx_outclock within the MSB of the
tx_out
data. Phase shift values beginning with 360° will position the rising edge of the
tx_outclock
in serial
bits after the MSB. For example, a phase shift of 540° will position the rising edge in the center of the bit
after the MSB (
Figure 9 ).
Figure 9: 540° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8
Use the Tx_outclock division factor drop-down list to set the
tx_outclock
frequency. Figure 10 shows a
x8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data
relationship).
Altera LVDS SERDES IP Core User Guide Altera Corporation
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Setting the Transmitter Output Clock Parameters 18
2014.08.18