Altera LVDS SERDES User Manual
Page 21
Where:
• RSKM—is the timing margin between the receiver's clock input and the data input SW.
• Time unit interval (TUI)—is the time period of the serial data (1/f
MAX
). Also known as the LVDS period
in the TimeQuest Timing Analyzer section in the Quartus II Compilation Report.
• SW—is the period of time that the input data must be stable to ensure that data is successfully sampled
by the LVDS receiver. The SW is a device property and varies with device speed grade.
• RCCS— is the timing difference between the fastest and slowest input transitions, including t
CO
variations
and clock skew. Specify RCCS by applying minimum and maximum
set_input_delay
constraints to
the receiver inputs, where RCCS is the difference between the maximum and minimum value.
The following figure shows the relationship between the RSKM, RCCS, and SW.
Figure 12: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
TUI
Time Unit Interval (TUI)
RCCS
Internal
Clock
Falling Edge
t
SW
(min)
Bit n
t
SW
(max)
Bit n
RCCS
RCCS
2
Receiver
Input Data
Transmitter
Output Data
Internal
Clock
Synchronization
External
Clock
Receiver
Input Data
Internal
Clock
External
Input Clock
Timing Budget
Timing Diagram
Clock Placement
SW
RCCS
RSKM
RSKM
SW
RSKM
RSKM
You must calculate the RSKM value to decide whether you can properly sample the data by the LVDS receiver
with the given data rate and device. A positive RSKM value indicates the LVDS receiver can properly sample
the data; a negative RSKM value indicates the receiver cannot properly sample the data.
The following example shows the RSKM calculation.
Altera Corporation
Altera LVDS SERDES IP Core User Guide
21
Non-DPA Mode RX and Receiver Skew Margin (RSKM)
ug_altera_lvds
2014.08.18