Adept system – Digilent 410-138P-KIT User Manual
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Genesys Reference Manual
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Once transferred, programming files are stored in SRAM-based memory cells within the FPGA. These
SRAM cells define the FPGA’s logic functions and circuit connections until they are erased, either by
removing power or asserting the PROG_B input.
FPGA configuration files transferred using the JTAG interface use the .bin and .svf file types, and BPI
files use the .bit, .bin, and .mcs file types. Xilinx’s ISE WebPack and EDK software can create .bit,
.svf, .bin, or .mcs files from VHDL, Verilog, or schematic-based source files (EDK is used for
MicroBlaze™ embedded processor-based designs). Digilent's Adept software and Xilinx's iMPACT
software can be used to program the Genesys board from a PC's USB port.
During FPGA programming, a .bit or .svf file is transferred from the PC to the FPGA using the USB-
JTAG port. When programming the ROM, a .bit, .bin, or .mcs file is transferred to the ROM in a two-
step process. First, the FPGA is programmed with a circuit that can transfer data from the USB-JTAG
port into the ROM, and then data is transferred to the ROM via the FPGA circuit (this complexity is
hidden and a simple “program ROM” interface is shown). After the ROM has been programmed, it can
automatically configure the FPGA at a subsequent power-on or reset event if the Mode jumpers are
set to the proper BPI mode. A programming file stored in the StrataFlash ROM will remain until it is
overwritten, regardless of power-cycle events.
Adept System
Adept and iMPACT USB Ports
The Genesys board includes two USB peripheral ports – one for Adept software and another for
Xilinx's iMPACT software. Either port can program the FPGA and StrataFlash, but Adept offers a
simplified user interface and many additional features such as automated board test and user-data
transfers. The Adept port is also compatible with iMPACT, if the Digilent Plug-In for Xilinx Tools is
installed on the host PC (download it free from the Digilent website).