Digilent 410-138P-KIT - Manual (Page 10)

Genesys Reference Manual
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The DDR2 interface follows the pinout and routing guidelines specified in the Xilinx Memory Interface
Generator (MIG) User Guide. The interface supports SSTL18 signaling, and all address, data, clocks,
and control signals are delay-matched and impedance-controlled. Address and control signals are
terminated through 47-ohm resistors to a 0.9V V
TT
, and data signals use the On-Die-Termination
(ODT) feature of the SODIMM. Two well-matched DDR2 clock signal pairs are provided to the
SODIMM that can be driven with low-skew clocks from the FPGA.
DQ[63:0]
DS[7:0] (differential)
14
64
16
AD[13:0]
I2C (SDA, SCK)
8
RAS#
CAS#
WE#
BA0
BA1
BA2
Clocks (differential)
6
S0#
S1#
ODT0
See Table
ODT1 F30
F31
J29
L29
R31
J30
G31
K29
E31
H30
Virtex 5
DDR2
SODIMM
DM[7:0]
2
x14