Digilent 410-138P-KIT - Manual (Page 16)

Genesys Reference Manual
www.digilentinc.com page 16 of 28
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners
Signal Name FPGA Pin Pin Function
AUD-BIT-CLK AH17 12.288MHZ serial clock output, driven at one-half the frequency of the
24.576MHz crystal input (XTL_IN)
AUD-SDI AE18 Serial Data In (to the FPGA) from the codec. SDI data consists of AC
’97 Link Input frames that contain both configuration and PCM audio
data. SDI data is driven on the rising edge of AUD-BIT-CLK.
AUD-SDO AG20 Serial Data Out (to the codec) from the FPGA. SDO data consists of AC
’97 Link Output frames that contain both configuration and DAC audio
data. SDO is sampled by the LM4550 on the falling edge of AUD-BIT-
CLK.
AUD-SYNC J9 AC Link frame marker and Warm Reset. SYNC (input to the codec)
defines AC Link frame boundaries. Each frame lasts 256 periods of
AUD-BIT-CLK. SYNC is normally a 48kHz positive pulse with a duty
cycle of 6.25% (16/256). SYNC is sampled on the rising edge of AUD-
BIT-CLK, and the codec takes the first positive sample of SYNC as
defining the start of a new AC Link frame. If a subsequent SYNC pulse
occurs within 255 AUD-BIT-CLK periods of the frame start it will be
ignored. SYNC is also used as an active high input to perform an
(asynchronous) Warm Reset. Warm Reset is used to clear a power
down state on the codec AC Link interface
AUD-RESET E12 Cold Reset. This active low signal causes a hardware reset which
returns the control registers and all internal circuits to their default
conditions. RESET must be used to initialize the LM4550 after Power
On when the supplies have stabilized. RESET also clears the codec
from both ATE and Vendor test modes. In addition, while active, it
switches the PC_BEEP mono input directly to both channels of the
LINE_OUT stereo output.
The EDK reference design (available on the Digilent website) leverages our custom AC-97 pcore to
accomplish several standard audio processing tasks such as recording and playing back audio data.
Serial Port
The Genesys board hosts two 2-wire RS-232 serial ports, one with a DB9F connector (for a DTE
connection), and one with a three-pin 100-mil header connector (including TX, RX, and GND). An
ST3232 level-shifting buffer is used to provide RS-232 signal levels on both ports. The serial port,
supported by standard EDK IP, is useful for user-data transfers as well as embedded processor
debugging.