Digilent 410-138P-KIT - Manual (Page 12)

Genesys Reference Manual
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A board test/demonstration program is loaded into the StrataFlash during manufacturing. That
configuration, also available on the Digilent webpage, can be used to demonstrate and check all of
the devices and circuits on the Genesys board.
Ethernet PHY
The Genesys board includes a Marvell Alaska Tri-mode PHY (the 88E1111) paired with a Halo
HFJ11-1G01E RJ-45 connector. Both MII and GMII interface modes are supported at 10/100/1000
Mb/s. Default settings used at power-on or reset are:
•
MII/GMII mode to copper interface
•
Auto Negotiation Enabled, advertising all speeds, preferring Slave
•
MDIO interface selected, PHY MDIO address = 00111
•
No asymmetric pause, no MAC pause, automatic crossover enabled
• Energy detect on cable disabled (Sleep Mode disabled), interrupt polarity LOW
The data sheet for the Marvell PHY is available from Marvell only with a valid NDA. Please contact
Marvell for more PHY-specific information.
EDK-based designs can access the PHY using either the xps_ethernetlite IP core for 10/100 Mbps
designs, or the xps_ll_temac IP core for 10/100/1000 Mbps designs. The xps_ll_temac IP core uses
the hard Ethernet MAC hardware core included in the Virtex 5 FPGA.
See Table
L19
N8
T6
N5
U10
Virtex 5
L4
K6
INT#
RESET#
COL
CRS
RX_DV
RX_CLK
RX_ER
GTX_CLK
TX_CLK
TX_ER
TX_EN
MDIO
8
25MHz
(from IDT5V9885)
MDC
CONFIG
7
0001101
CLK
See Table
L5
J20
J16
R8
T10
RXD
TXD
8
8
Marvell M88E1111
x14
Halo HFJ11
Integrated magnetics
RXD Signals
RXD0: N7
RXD1: R6
RXD2: P6
RXD3: P5
RXD4: M7
RXD5: M6
RXD6: M5
RXD7: L6
TXD Signals
TXD0: J5
TXD1: G5
TXD2: F5
TXD3: R7
TXD4: T8
TXD5: R11
TXD6: T11
TXD7: U7