Cypress Perform CY7C68013 - Manual (Page 47)

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 47 of 62
There is no specific timing requirement that should be met for
asserting PKTEND pin to asserting SLWR. PKTEND can be
asserted with the last data value clocked into the FIFOs or there-
after. The setup time t
SPE
and the hold time t
PEH
must be met.
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one byte
or word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and it is required to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte or word packet committed manually
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet.
Figure 23 shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 23 shows a scenario where two packets are committed.
The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet being
committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
Figure 23. Slave FIFO Synchronous Write Sequence and Timing Diagram
[20]
10.12 Slave FIFO Asynchronous Packet End Strobe
Figure 24. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
[20]
IFCLK
SLWR
DATA
t
IFCLK
>= t
SWR
>= t
WRH
X-2
PKTEND
X-3
t FAH
t
SPE t PEH
FIFOADR
t
SFD
t SFD t SFD
X-4
t FDH t
FDH
t FDH
t
SFA
1 X
t SFD
t SFD t SFD
X-1
t
FDH t FDH
t
FDH
At least one IFCLK cycle
Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters [23]
Parameter Description Min Max Unit
t
PEpwl
PKTEND Pulse Width LOW 50 ns
t
PWpwh
PKTEND Pulse Width HIGH 50 ns
t
XFLG
PKTEND to FLAGS Output Propagation Delay 115 ns
FLAGS
t
XFLG
PKTEND t
PEpwl
t
PEpwh
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