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Table 12. fx2lp register summary (continued) – Cypress Perform CY7C68013 User Manual

Page 35

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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *L

Page 35 of 62

BE

1

GPIFSGLDATLX

[13]

GPIF Data L w/ Trigger

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

BF

1

GPIFSGLDATL-
NOX

[13]

GPIF Data L w/ No Trigger D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx R

C0

1

SCON1

[13]

Serial Port 1 Control (bit
addressable)

SM0_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

00000000 RW

C1

1

SBUF1

[13]

Serial Port 1 Data Buffer D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

C2

6

reserved

C8

1

T2CON

Timer/Counter 2 Control
(bit addressable)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000 RW

C9

1

reserved

CA

1

RCAP2L

Capture for Timer 2, au-
to-reload, up-counter

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CB

1

RCAP2H

Capture for Timer 2, au-
to-reload, up-counter

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CC

1

TL2

Timer 2 reload L

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CD

1

TH2

Timer 2 reload H

D15

D14

D13

D12

D11

D10

D9

D8

00000000 RW

CE

2

reserved

D0

1

PSW

Program Status Word (bit
addressable)

CY

AC

F0

RS1

RS0

OV

F1

P

00000000 RW

D1

7

reserved

D8

1

EICON

[13]

External Interrupt Control SMOD1

1

ERESI

RESI

INT6

0

0

0

01000000 RW

D9

7

reserved

E0

1

ACC

Accumulator (bit address-
able)

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

E1

7

reserved

E8

1

EIE

[13]

External Interrupt En-
able(s)

1

1

1

EX6

EX5

EX4

EI²C

EUSB

11100000 RW

E9

7

reserved

F0

1

B

B (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

F1

7

reserved

F8

1

EIP

[13]

External Interrupt Priority
Control

1

1

1

PX6

PX5

PX4

PI²C

PUSB

11100000 RW

F9

7

reserved

Table 12. FX2LP Register Summary (continued)

Hex

Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

r = read-only bit

w = write-only bit

b = both read/write bit

R = all bits read-only
W = all bits write-only

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