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Cypress CY14E102L User Manual

Features, Functional description, Logic block diagram

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ADVANCE

CY14E102L, CY14E102N

2-Mbit (256K x 8/128K x 16) nvSRAM

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document Number: 001-45755 Rev. *A

Revised June 27, 2008

Features

15 ns, 20 ns, 25 ns, and 45 ns access times

Internally organized as 256K x 8 (CY14E102L) or 128K x 16
(CY14E102N)

Hands off automatic STORE on power down with only a small
capacitor

STORE to QuantumTrap

nonvolatile elements initiated by

software, device pin, or AutoStore

on power down

RECALL to SRAM initiated by software or power up

Infinite read, write, and recall cycles

200,000 STORE cycles to QuantumTrap

20 year data retention

Single 5V +10% operation

Commercial and Industrial temperatures

48-pin FBGA, 44 and 54-pin TSOP II packages

Pb-free and RoHS compliance

Functional Description

The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data reside in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.

Note

1. Address A

0

- A

17

and Data DQ0 - DQ7 for x8 configuration, Address A

0

- A

16

and Data DQ0 - DQ15 for x16 configuration.

A

0

- A

17

Address

WE

OE

CE

V

CC

V

SS

V

CAP

DQ0 - DQ7

HSB

CY14E102L

BHE

BLE

Logic Block Diagram

[1]

[1]

CY14E102N

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