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Cypress CY14E256L User Manual

Features, Functional description, Logic block diagram

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CY14E256L

256 Kbit (32K x 8) nvSRAM

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document Number: 001-06968 Rev. *F

Revised January 30, 2009

Features

25 ns, 35 ns, and 45 ns access times

Pin compatible with STK14C88

Hands off automatic STORE on power down with external 68
µF capacitor

STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down

RECALL to SRAM initiated by software or power up

Unlimited READ, WRITE, and RECALL cycles

1,000,000 STORE cycles to QuantumTrap

100 year data retention to QuantumTrap

Single 5V+10% operation

Commercial and industrial temperature

32-pin SOIC and CDIP (300 mil) packages

RoHS compliance

Functional Description

The Cypress CY14E256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT

BUFFERS

OE

CE
WE

HSB

V

CC

V

CAP

A

13

-

A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

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