Cypress Perform CY7C68013 User Manual
Cypress Hardware
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• 408-943-2600
Document #: 38-08032 Rev. *L
Revised February 8, 2008
1. Features (CY7C68013A/14A/15A/16A)
■
USB 2.0 USB IF high-speed certified (TID # 40460272)
■
Single chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
■
Fit, form and function compatible with the FX2
❐
Pin compatible
❐
Object-code-compatible
❐
Functionally compatible (FX2LP is a superset)
■
Ultra Low power: I
CC
no more than 85 mA in any mode
❐
Ideal for bus and battery powered applications
■
Software: 8051 code runs from:
❐
Internal RAM, which is downloaded via USB
❐
Internal RAM, which is loaded from EEPROM
❐
External memory device (128 pin package)
■
16 KBytes of on-chip Code/Data RAM
■
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐
Buffering options: double, triple, and quad
■
Additional programmable (BULK/INTERRUPT) 64 byte
endpoint
■
8-bit or 16-bit external data interface
■
Smart Media Standard ECC generation
■
GPIF (General Programmable Interface)
❐
Enables direct connection to most parallel interfaces
❐
Programmable waveform descriptors and configuration reg-
isters to define waveforms
❐
Supports multiple Ready (RDY) inputs and Control (CTL) out-
puts
■
Integrated, industry standard enhanced 8051
❐
48 MHz, 24 MHz, or 12 MHz CPU operation
❐
Four clocks per instruction cycle
❐
Two USARTS
❐
Three counter/timers
❐
Expanded interrupt system
❐
Two data pointers
■
3.3V operation with 5V tolerant inputs
■
Vectored USB interrupts and GPIF/FIFO interrupts
■
Separate data buffers for the Setup and Data portions of a
CONTROL transfer
■
Integrated I
2
C controller, runs at 100 or 400 kHz
■
Four integrated FIFOs
❐
Integrated glue logic and FIFOs lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
Uses external clock or asynchronous strobes
❐
Easy interface to ASIC and DSP ICs
■
Available in Commercial and Industrial temperature grade (all
packages except VFBGA)
Document Outline
- 1. Features (CY7C68013A/14A/15A/16A)
- 2. Applications
- 3. Functional Overview
- 3.1 USB Signaling Speed
- 3.2 8051 Microprocessor
- 3.3 I2C Bus
- 3.4 Buses
- 3.5 USB Boot Methods
- 3.6 ReNumeration™
- 3.7 Bus-powered Applications
- 3.8 Interrupt System
- 3.9 Reset and Wakeup
- 3.10 Program/Data RAM
- 3.11 Register Addresses
- 3.12 Endpoint RAM
- 3.13 External FIFO Interface
- 3.14 GPIF
- 3.15 ECC Generation[7]
- 3.16 USB Uploads and Downloads
- 3.17 Autopointer Access
- 3.18 I2C Controller
- 3.19 Compatible with Previous Generation EZ-USB FX2
- 3.20 CY7C68013A/14A and CY7C68015A/16A Differences
- 4. Pin Assignments
- 5. Register Summary
- 6. Absolute Maximum Ratings
- 7. Operating Conditions
- 8. Thermal Characteristics
- 9. DC Characteristics
- 10. AC Electrical Characteristics
- 10.1 USB Transceiver
- 10.2 Program Memory Read
- 10.3 Data Memory Read
- 10.4 Data Memory Write
- 10.5 PORTC Strobe Feature Timings
- 10.6 GPIF Synchronous Signals
- 10.7 Slave FIFO Synchronous Read
- 10.8 Slave FIFO Asynchronous Read
- 10.9 Slave FIFO Synchronous Write
- 10.10 Slave FIFO Asynchronous Write
- 10.11 Slave FIFO Synchronous Packet End Strobe
- 10.12 Slave FIFO Asynchronous Packet End Strobe
- 10.13 Slave FIFO Output Enable
- 10.14 Slave FIFO Address to Flags/Data
- 10.15 Slave FIFO Synchronous Address
- 10.16 Slave FIFO Asynchronous Address
- 10.17 Sequence Diagram
- 11. Ordering Information
- 12. Package Diagrams
- 13. PCB Layout Recommendations
- 14. Quad Flat Package No Leads (QFN) Package Design Notes
- Logic Block Diagram
- Logic Block Diagram