Cypress Perform CY7C68013 - Manual (Page 40)

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 40 of 62
10.4 Data Memory Write
Figure 14. Data Memory Write Timing Diagram
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
t
STBL
t
STBH
data out
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
data out
Stretch = 1
t
ON1
t
SCSL
t
AV
CS#
t
ON1
CS#
Table 17. Data Memory Write Parameters
Parameter Description Min Max Unit Notes
t
AV
Delay from Clock to Valid Address 0 10.7 ns
t
STBL
Clock to WR Pulse LOW 0 11.2 ns
t
STBH
Clock to WR Pulse HIGH 0 11.2 ns
t
SCSL
Clock to CS Pulse LOW 13.0 ns
t
ON1
Clock to Data Turn-on 0 13.1 ns
t
OFF1
Clock to Data Hold Time 0 13.1 ns
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