Cirrus Logic CDB8422 - Manual (Page 8)

8 DS692DB2
CDB8422
2.2.2 AES3/EBU In to S/PDIF and PCM Out
The CS8422’s AES3/EBU receiver and SRC output performance can be tested by loading the “AES3 In
to SPDIF and PCM Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in
Figure 3 .
Digital AES3/EBU input is provided by the XLR jack J19 to the RXP0 and RXN0 pins of the CS8422. The
script configures the CS8422’s internal circuitry to send the input audio data through its SRC to serial out-
put port 1. This data is presented as PCM audio at header J24 and S/PDIF audio at J27 (coaxial) and J28
(optical). The input data is also passed through (SRC is bypassed) to serial output port 2. This data is
presented as PCM audio at header J25. Refer to
Section 2.3 for details on software configuration.
Figure 3. AES3/EBU In to S/PDIF and PCM Out
CS8422
CS8406
S/PDIF Tx
(SLAVE)
Buffer Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
OSCLK1
OLRCK1
SDOUT1
OSCLK2
OLRCK2
SDOUT2
ISCLK
ILRCK
SDIN
OSCLK2
OLRCK2
SDOUT2
OSCLK1
OLRCK1
SDOUT1
Optical
S/PDIF
Out
J28
AND
J27
J31
Coaxial
S/PDIF
Out
S/PDIF
OUT
RMCK
OMCK
MCLK OUT
MCLK OUT
J19
J21
AES3/EBU
In
J29
RXP0
RXP1
RXN0
RXN1
PCM Out
through SRC
PCM Out
no SRC